Experimental Evaluation of Dynamic Scheduling for Parallel Logic Simulation Using Benchmark Circuits

Tadashi SEKO  Tohru KIKUNO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E77-A   No.11   pp.1910-1912
Publication Date: 1994/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
parallel logic simulation,  processor scheduling,  

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Summary: 
We discuss a processor scheduling problem for parallel logic simulation of combinational circuits. In the processor scheduling problem, to be discussed in this paper, for logic simulation using time–first method, the time needed for each gate evaluation is not given beforehand, and is not constant. This feature distinguishes the processor scheduling problem from typical task scheduling problems. First, we devise newly Algorithm MET to solve the processor scheduling problem. The key idea of Algorithm MET is to determine processor scheduling incrementally and dynamically. Then, experimental evaluations using well–known twelve benchmark combinational circuits show the usefulness of Algorithm, MET, compared with conventional static algorithms. We believe that this is a first step to implement parallel logic simulation of combinational circuits.