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Dependence of CMOS/SIMOX Inverter Delay Time on Gate Overlap Capacitance
Takakuni DOUSEKI Kazuo AOYAMA Yasuhisa OMURA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/08/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
CMOS, SIMOX, inverter, gate overlap, capacitance,
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This paper describes the dependence of the delay time of a CMOS/SIMOX inverter on the gate-overlap capacitance. An analytical delay-time equation for the CMOS/SIMOX inverter, which includes the gate-overlap capacitance, is derived. This equation shows that the feed-forward effect dominates the characteristics of inverters with a small fanout. The validity of the delay-time equation is confirmed by the comparison to experimental measurements of 0.4-µm CMOS/SIMOX devices. Moreover, a sensitivity analysis shows that it is very important to reduce the gate-drain overlap capacitance for fabricating high-speed scaled-down CMOS/SIMOX devices.