A Programmable Parallel Digital Neurocomputer

Yoshiyuki SHIMOKAWA  Yutaka FUWA  Naruhiko ARAMAKI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.7   pp.1197-1205
Publication Date: 1993/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural network,  neurocomputer,  neuro chip,  ASIC,  

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Summary: 
We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.