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A Digital Neural Network Coprocessor with a Dynamically Reconfigurable Pipeline Architecture
Takayuki MORISHITA Youichi TAMURA Takami SATONAKA Atsuo INOUE Shin-ichi KATSU Tatsuo OTSUKI
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
neural network, digital, back propagation learning,
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We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer, network by means of a network decomposition and a distributed processing approach.