Development and Fabrication of Digital Neural Network WSIs

Minoru FUJITA  Yasushi KOBAYASHI  Kenji SHIOZAWA  Takahiko TAKAHASHI  Fumio MIZUNO  Hajime HAYAKAWA  Makoto KATO  Shigeki MORI  Tetsuro KASE  Minoru YAMADA  

IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.7   pp.1182-1190
Publication Date: 1993/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
neural network,  WSI,  CMOS,  electron-beam direct-writing,  

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Digital neural networks are suitable for WSI implementation because their noise immunity is high, they have a fault tolerant structure, and the use of bus architecture can reduce the number of interconnections between neurons. To investigate the feasibility of WSIs, we integrated either 576 conventional neurons or 288 self-learning neurons on a 5-inch wafer, by using 0.8-µm CMOS technology and three metal layers. We also developed a new electron-beam direct-writing technology which enables easier fabrication of VLSI chips and wafer-level interconnections. We fabricated 288 self-learning neuron WSIs having as many as 230 good neurons.