Hardware Architecture for Kohonen Network

Hidetoshi ONODERA  Kiyoshi TAKESHITA  Keikichi TAMARU  

IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.7   pp.1159-1166
Publication Date: 1993/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Neural Networks and Chips
neural network,  Kohonen network,  massively parallel computation,  content addressable memory,  

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We propose a fully digital architecture for Kohonen network suitable for VLSI implementation. The proposed architecture adopts a functional memory type parallel processor (FMPP) architecture which has a structure similar to a content addressable memory (CAM). One word of CAM is regarded as a processing element and a group of elements forms a neuron. All processing elements execute the same operation in bit-serial but in processor-parallel. Thus the number of instructions for realizing the network algorithm is independent of the number of neurons in the network. With reference to a previously reported CAM, we estimate a network with 96 neurons for speech recognition could be integrated on three chips using a 1.2 µm process, and it operates 50 times faster than a sequential hardware. Owing to its highly regular structure of memories, the proposed hardware architecture is well compatible with current VLSI technology.