A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture

Tsuguo KOBAYASHI  Kazutaka NOGAMI  Tsukasa SHIROTORI  Yukihiro FUJIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.5   pp.863-867
Publication Date: 1993/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
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Summary: 
This paper describes two new power-saving schemes for high-performance VLSI's with a large-scale memory and many interface signals. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces dc current in interface circuits receiving TTL-high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM.