A 10-b 300-MHz Interpolated-Parallel A/D Converter

Hiroshi KIMURA  Akira MATSUZAWA  Takashi NAKAMURA  Shigeki SAWADA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.5   pp.778-786
Publication Date: 1993/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
A/D converter,  parallel,  interpolation,  high speed,  high resolution,  linearity,  circuit,  bipolar,  submicrometer,  folding,  encoder,  logic,  

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Summary: 
This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.