A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and Source-Coupled Transistors Operable on Low Supply Voltage

Katsuji KIMURA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.5   pp.714-737
Publication Date: 1993/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
low voltage,  analog,  four-quadrant multiplier,  bipolar LSI,  MOS LSI,  

Full Text: PDF>>
Buy this Article




Summary: 
Novel circuit design techniques for bipolar and MOS four-quadrant analog multipliers operable on low supply voltage are described. There are three design techniques for multipliers operable on low supply voltage. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. Bipolar and MOS four-quadrant analog multipliers proposed in this paper consist of transistor-pairs with different transistor sizes (i.e. emitter areas or gate W/L values are different), transistor-pairs with the same bias offset or multitail cells (i.e. quadritail cells and an octotail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to the multipliers when the multiplication method is based on the quarter-square technique. These multipliers all have satisfiable multiplication characteristics with four-quadrant operations in analog signal processing, whether implemented in bipolar technology or implemented in MOS technology.