Process and Device Technologies of CMOS Devices for Low-Voltage Operation

Masakazu KAKUMU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.5   pp.672-680
Publication Date: 1993/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)
Category: 
Keyword: 
CMOS,  SOI,  SIMOX,  MOSFET,  low-voltage,  low-temperature,  threshold voltage high-speed,  power-supply voltage,  subthreshold current,  circuit performance,  power dissipation,  

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Summary: 
Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-seed operation of the COMS device at low-voltage.