High-Speed SOI Bipolar Transistors Using Bonding and Thinning Techniques

Manabu KOJIMA  Atsushi FUKURODA  Tetsu FUKANO  Naoshi HIGAKI  Tatsuya YAMAZAKI  Toshihiro SUGII  Yoshihiro ARIMOTO  Takashi ITO  

IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.4   pp.572-576
Publication Date: 1993/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
SOI bipolar transistors,  thin buried layer,  wafer bonding,  selective polishing,  

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We propose a high-speed SOI bipolar transistor fabricated using bonding and thinning techniques. It is important to replace SOI area except for devices with thick SiO2 to reduce parasitic capacitance. A thin SOI film with a thin buried layer helps meet this requirement. We formed a 1-µm-thick SOI film with a 0.7-µm-thick buried layer by ion implantation before wafer bonding pulse-field-assisted bonding and selective polishing. Devices were completely isolated by thick SiO2 using a thin SOI film and the LOCOS process. We fabricated epitaxial base transistors (EBTs) on bonded SOI. Our transistors had a cutoff frequency of 32 GHz.