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A Capacitor over Bit-Line (COB) Stacked Capacitor Cell Using Local Interconnect Layer for 64 MbDRAMs
Naoki KASAI Masato SAKAO Toshiyuki ISHIJIMA Eiji IKAWA Hirohito WATANABE Toshio TAKESHIMA Nobuhiro TANABE Kazuo TERADA Takamaro KIKKAWA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
DRAM, memory cell, stacked capacitor, local interconnect,
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A new capacitor over bit-line (COB) stacked capacitor memory cell was developed using a local interconnect poly-silicon layer to arrange a capacitor contact between bit-lines. This memory cell enables usable capacitor area to increase and capacitor contact hole depth to decrease. The hemispherical grain (HSG) silicon, whose effective surface area is twice that of ordinary poly-silicon, was utilized for the storage node to increase the storage capacitance without increasing the storage node height. The feasibility of achieving a 1.8 µm2 memory cell with 30 fF storage capacitance using a 7 nm-SiO2-equivalent dielectric film and a 0.5 µm-high HSG storage node has been verified for 64 MbDRAMs by a test memory device using a 0.4 µm CMOS process.