IEICE Trans - A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation

A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation

Masahiro SHIMIZU  Takehisa YAMAGUCHI  Masahide INUISHI  Katsuhiro TSUKAMOTO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.4   pp.532-540
Publication Date: 1993/04/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword:
MOS transistor,  shallow junction,  salicide,  titanium,

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Summary:
A novel CMOS structure has been developed using Ti-salicide PSD transistor formed by a new self-aligned method. Both N-channel and P-channel PSD transistors exhibit excellent short-channel behaviors down to the sub-half-micrometer region with shallow S/D junctions formed by dopant diffusion from polysilicons. New salicide process has been developed for the PSD structure and can effectively reduce the sheet resistances of the S/D polysilicon and the polysilicon gate to as low as 4

. As a result, the low resistive local interconnects can be successfully implemented by the Ti-salicide S/D polysilicon merged with contacts by self-alignment. More-over it is found that shallow Ti-salicide S/D junctions with the PSD structure can achieve approximately 1

2 orders of magnitude lower area leakage current than that of the conventional implanted S/D junctions by eliminating implanted damage and preventing penetration of silicide into junctions with the elevated structure of S/D polysilicon layer. Furthermore CMOS ring oscillators having PSD transistors with an effective channel length of 0.4 µm were fabricated using the salicided S/D polysilicon as a local interconnect between the N⁺ and the P⁺ regions, and successfully operated with a propagation delay time of 50 ps/stage at a supply voltage of 5 V.