A Highly Drivable CMOS Design with Very Narrow Sidewall and Novel Channel Profile for 3.3 V High Speed Logic Application

Jiro IDA  Satoshi ISHII  Youko KAJITA  Tomonobu YOKOYAMA  Masayoshi INO  

IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.4   pp.525-531
Publication Date: 1993/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
CMOS,  LDD,  hot-carrier-reliability,  multiplier,  

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A CMOS design to achieve high drivability is examined for lower power supply voltage in 0.5 µm ULSI. The design consists of two points. (1) A very narrow (50 nm) sidewall is used to achieve high drivability and also to obtain hot-carrier-reliability. (2) A retrograded channel profile with NMOS and PMOS is designed to achieve high drivability and also to reduce short channel effect. It is shown that the propagation delay times (tpd) of a unloaded Inverter and a loaded 2-way NAND gate are improved 30% with the newly designed CMOS, compared with the conventionally designed CMOS. It is also proved that the tpd keeps the scaling trend of the previous-5 V-era even in 3.3 V-era by adapting the newly designed CMOS. Moreover, 7.1 ns multiplication time of 1616-bit multiplier is obtained under 0.5 µm design rule.