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High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
Shigeo KUNINOBU Tamotsu NISHIYAMA Takashi TANIGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
multiplier, divider, redundant binary, microprocessor,
Full Text: PDF(852.9KB)>>
We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.