Proposed Optoelectronic Cascadable Multiplier on GaAs LSI

Kazutoshi NAKAJIMA  Yoshihiko MIZUSHIMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.1   pp.118-123
Publication Date: 1993/01/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Opto-Electronics and LSI)
Category: Integration of Opto-Electronics and LSI Technologies
Keyword: 
optoelectronic logic,  metal-semiconductor-metal photodetector,  half-adder,  multiplier,  

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Summary: 
An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.