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Proposed Optoelectronic Cascadable Multiplier on GaAs LSI
Kazutoshi NAKAJIMA Yoshihiko MIZUSHIMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/01/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Opto-Electronics and LSI)
Category: Integration of Opto-Electronics and LSI Technologies
optoelectronic logic, metal-semiconductor-metal photodetector, half-adder, multiplier,
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An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.