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Single-Board SIMD Processors Using Gate-Array LSIs for Parallel Processing
Toshio KONDO Yoshimasa KIMURA Noboru SONEHARA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
parallel processor, SIMD, gate-array, tree network,
Full Text: PDF(689KB)>>
We have developed an SIMD processor on a double-height VME board. We achieved a good balance between cost and performance by combining four identical gate-array LSIs in the processor array with a 16-bit degital signal processor (DSP), standard dynamic random-access memories (DRAMs) and other peripherals. The gate-array LSIs have 168-bit processing elements (PEs), each containing a one-bit processing block and a serial multiplier. This PE structure offers high-level bit processing capability and peak performance of 512 million operations per second (MOPS) for 8-bit multiply and accumulate operations. Effective performance of more than 300 MOPS for 8-bit array data processing is achieved by using an LSI structure tuned to the DRAM access rate, although the processing speed is reduced by the DRAM access bottleneck. The LSIs also have two unique additional hardware structures that speed up various array data processes. One is an inter-PE routing register array for supporting a transmission, rotation and memory access path. The other is a tree-structure network for propagating operations among PEs. With these cost-effective structures, the SIMD processor is expected to be widely used for two-dimensional data processing, such as image processing and pattern recognition.