Durable and Low Power-Loss Semiconductor Devices for Specific Automotive Applications

Tsutomu MATSUSHITA  Teruyoshi MIHARA  Masakatsu HOSHI  Minoru AOYAGI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.12   pp.1819-1826
Publication Date: 1993/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
power MOS,  on-resistance,  avalanche ASO,  intelligent power device,  

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Summary: 
We have developed new DMOS FET (DMOS) and intelligent power devices (IPD) specified for automotive load driving. Their features are extra-high surge immunity and low on-resistance. MOS power semiconductor devices are the most suitable for driving high speed and large current loads in future car electronics, but their high cost is the main obstacle preventing their implementation. To cut the total system cost, we have tried to enhance surge immunity of power semiconductor devices, at the same time reducing ON resistance, which enables us to omit external protection. Enhanced avalanche power dissipation also enables us to lower the breakdown voltage of the device, which also brings lower on-resistance. The drain to source avalanche immunity of vertical type DMOS (VDMOS) has been sharply improved by using the parasitic PN junction of the channel diffusion region as the cellular zener diode. Avalanche power dissipation energy per unit area of this durable DMOS is 10 to 100 times higher than that of conventional VDMOSs. Although the breakdown voltage of this device is only 30V, no external protection device is required in automotive applications. Several fault phenomena which might occur in this device are also described. Two types of IPDs are proposed in this paper. One is a durable and low-cost high-side switch IPD, whose enhanced surge immunity of IC section from VDD line transient is verified by prototypes. Simplification of the fabrication process has also been achieved by lowering its breakdown voltage. The other is an extra-low on-resistance H-bridge IPD. Major on-resistance reduction of an output lateral type DMOS (LDMOS) is achieved because the cell-array structure is realized by applying 2-layer electrode technology to the power section. The on-resistance per unit area of this LDMOS is almost equal to that of VDMOSs in the same voltage class.