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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI Publication IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1657-1664 Publication Date: 1993/11/25 Online ISSN: DOI: Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy, Full Text: PDF>>
Summary: This paper describes a bitline control circuit and redundancy technique for high-density dynamic content addressable memories (CAMs). The proposed bitline control circuit can efficiently manage a dynamic CAM cell accompanied by complex operations; that is, a refresh operation, a masked search operation, and partial writing, in addition to normal read/write/search operations. By adding a small supplementary circuit to the bitline control circuit, a circuit scheme with redundancy which prevents disabled column circuits from affecting a match operation can also be obtained. These circuit technologies achieve higher-density dynamic CAMs than conventional static CAMs. These technologies have been successfully applied to a 288-kbit CAM with a typical cycle time of 150 ns. | |||||
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