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High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT),
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New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.