Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement

Ken-ichi IMAMIYA  Jun-ichi MIYAMOTO  Nobuaki OHTSUKA  Naoto TOMITA  Yumiko IYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E76-C    No.11    pp.1626-1631
Publication Date: 1993/11/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: Non-volatile Memory
redundancy,  memory,  yield,  EPROM,  

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The method to optimize redundancy scheme for memory devices is proposed. Yield for new generation memories is predicted by failure mode analysis of previous generation memories. Fabrication line improvement and chip area penalty by the redundancy are taken into account for this yield prediction. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction.