Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time

Kenichi OHHATA  Yoshiaki SAKURAI  Hiroaki NAMBU  Kazuo KANETANI  Youji IDEI  Toshirou HIRAMOTO  Nobuo TAMBA  Kunihiko YAMAGUCHI  Masanori ODAKA  Kunihiko WATANABE  Takahide IKEDA  Noriyuki HOMMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C    No.11    pp.1611-1619
Publication Date: 1993/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
ECL-CMOS SRAM,  64-kb,  noise reduction,  crosstalk,  

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Summary: 
An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.