For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time
Kenichi OHHATA Yoshiaki SAKURAI Hiroaki NAMBU Kazuo KANETANI Youji IDEI Toshirou HIRAMOTO Nobuo TAMBA Kunihiko YAMAGUCHI Masanori ODAKA Kunihiko WATANABE Takahide IKEDA Noriyuki HOMMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
ECL-CMOS SRAM, 64-kb, noise reduction, crosstalk,
Full Text: PDF>>
An ECL-CMOS SRAM technology is proposed which features a combination of ECL word drivers, ECL write circuits and low-voltage CMOS cells. This technology assures both ultra-high-speed and high-density. In the ECL-CMOS SRAM,various kinds of noise generated during the write cycle seriously affect the memory performance, because it has much faster access than conventional SRAMs. To overcome this problem, we propose three noise reduction techniques; a noise reduction clamp circuit, an emitter follower with damping capacitor and a twisted bit line structure with "normally on" equalizer. These techniques allow fast accese and cycle times. To evaluate these techniques, a 64-kb SRAM chip was fabricated using 0.5-µm BiCMOS technology. This SRAM has a short cycle time of 2 ns and a very fast access time of 1.5 ns. Evaluation proves the usefulness of these techniques.