A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories

Masaki TSUKUDA  Kazutami ARIMOTO  Mikio ASAKURA  Hideto HIDAKA  Kazuyasu FUJISHIMA  

IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.11   pp.1589-1594
Publication Date: 1993/11/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
reduction of design TAT,  design methodology,  ULSI memory,  

Full Text: PDF>>
Buy this Article

We propose a smart design methodology for advanced ULSI memories to reduce the turn around time(TAT) for circuit revisions with no area penalty. This methodology was executed by distributing extra gate-arrays, which were composed of the n-channel and p-channel transistors, under the power line and the signal line. This method was applied to the development of a 16 Mb DRAM with double metal wiring. The design TAT can be reduced to 1/8 using 1500 gates. This design methodology has been confirmed to be very effective.