Trends in Capacitor Dielectrics for DRAMs

Akihiko ISHITANI  Pierre-Yves LESAICHERRE  Satoshi KAMIYAMA  Koichi ANDO  Hirohito WATANABE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E76-C   No.11   pp.1564-1581
Publication Date: 1993/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
capacitor,  dielectrics,  Si3N4,  Ta2O5,  high permittivity materials,  256 Mbit,  1 Gbit,  DRAM,  

Full Text: PDF(1.8MB)>>
Buy this Article




Summary: 
Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.