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Trends in Capacitor Dielectrics for DRAMs
Akihiko ISHITANI Pierre-Yves LESAICHERRE Satoshi KAMIYAMA Koichi ANDO Hirohito WATANABE
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories)
capacitor, dielectrics, Si3N4, Ta2O5, high permittivity materials, 256 Mbit, 1 Gbit, DRAM,
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Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.