For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A New Proposal for Inverter Delay Improvement on CMOS/SOI Future Technology
M.O. LEE Kunihiro ASADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/10/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
TPD time-dependent gate capacitance(TDGC), SOI, deep sub-micrometer, CMOS, poly-si gate thickness(tm), ring oscillator,
Full Text: PDF>>
High performances of CMOS/SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (tm), and experiments are verified and proposed. It is shown that the tm and gate oxide thickness(tox) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time(TPD). Contributions of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the tox remains constant. It is concluded that the TPDs by reducing the tm to zero are improved up to about two times faster than typically fabricated ring oscillator at 350 nm of the tm in deep-submicrometer gate CMOS/SIMOX inverters at room temperature.