A High-Speed ATM Switching Architecture Using Small Shared Switch Blocks

Ken-ichi ENDO  Naoaki YAMANAKA  

IEICE TRANSACTIONS on Communications   Vol.E76-B   No.7   pp.736-740
Publication Date: 1993/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1992 IEICE Fall Conference and the 1993 IEICE Spring Conference)
ATM,  B-ISDN,  ring arbitrator,  contention control,  matrix switch,  high-speed,  

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This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.