A High-Speed ATM Switch with Input and Cross-Point Buffers

Yukihiro DOI  Naoaki YAMANAKA  

Publication
IEICE TRANSACTIONS on Communications   Vol.E76-B   No.3   pp.310-314
Publication Date: 1993/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Switching and Communication Processing
Keyword: 
switching and communication processing ATM,  B-ISDN,  switch,  cell buffering,  

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Summary: 
This letter describes a new input and cross-point buffering matrix switching architecture for high-speed ATM switching systems. The proposed switch has input queuing buffers at each input port, and small size buffers for output port arbitration at each cross-point. These two types of buffers share loads using a simple and high-speed retry algorithm. Hardware size is only half that of conventional cross-point buffering switches. In addition, the switch achieves high-throughput at a condition that the switching speed matches the input and output port speed. This switch is expected to enable the development of high-speed ATM switching systems with each port supporting speeds in excess of 1Gbit/s.