An Architecture for High Speed Array Multiplier

Farhad Fuad ISLAM  Keikichi TAMARU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E76-A   No.8   pp.1326-1333
Publication Date: 1993/08/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Computer Aided Design (CAD)
binary multiplication,  array multipler,  VLSI architecture,  

Full Text: PDF(656.7KB)>>
Buy this Article

High speed multiplication of two n-bit numbers plays an important role in many digital signal processing applications. Traditional array and Wallace multipliers are the most widely used multipliers implemented in VLSI. The area and time (=latency) of these two multipliers depend on operand bit-size, n. For a particular bit-size, they occupy fixed positions in some graph which has area and time along the x and y-axes respectively. However, many applications require a multiplier which has an 'intermediate' area-time characteristics with the above two traditional multipliers occupying two extreme ends of above mentioned area-time curve. In this paper, we propose such an intermediate multiplier which trades off area for time. It has higher speed (i.e., less latendy) but more area than a traditional array multiplier. Whereas when compared with a traditional Wallace multiplier, it has lower speed and area. The attractive point of our multiplier is that, it resembles an array multiplier in terms of regularity in placement and inter-connection of unit computation cells. And its interesting feature is that, in contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts among its computation cells. In this paper, we investigate on the area-time complexity of our proposed multiplier and discuss on its characteristics while comparing with some contemporary multiplers in terms of latency, area and wiring complexity.