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An Architecture for High Speed Array Multiplier
Farhad Fuad ISLAM Keikichi TAMARU
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E76A
No.8
pp.13261333 Publication Date: 1993/08/25
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: binary multiplication, array multipler, VLSI architecture,
Full Text: PDF(656.7KB)>>
Summary:
High speed multiplication of two nbit numbers plays an important role in many digital signal processing applications. Traditional array and Wallace multipliers are the most widely used multipliers implemented in VLSI. The area and time (=latency) of these two multipliers depend on operand bitsize, n. For a particular bitsize, they occupy fixed positions in some graph which has area and time along the x and yaxes respectively. However, many applications require a multiplier which has an 'intermediate' areatime characteristics with the above two traditional multipliers occupying two extreme ends of above mentioned areatime curve. In this paper, we propose such an intermediate multiplier which trades off area for time. It has higher speed (i.e., less latendy) but more area than a traditional array multiplier. Whereas when compared with a traditional Wallace multiplier, it has lower speed and area. The attractive point of our multiplier is that, it resembles an array multiplier in terms of regularity in placement and interconnection of unit computation cells. And its interesting feature is that, in contrast to a traditional array multiplier, it computes by introducing multiple computation wave fronts among its computation cells. In this paper, we investigate on the areatime complexity of our proposed multiplier and discuss on its characteristics while comparing with some contemporary multiplers in terms of latency, area and wiring complexity.

