Performance Evaluation of Super High Definition Lmage Processing on a Parallel DSP System

Tomoko SAWABE  Tatsuya FUJII  Tetsurou FUJII  Sadayasu ONO  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E76-A   No.8   pp.1308-1315
Publication Date: 1993/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from the 7th Digital Signal Processing Symposium)
Category: Image Processing
Keyword: 
parallel DSP system,  super high definition image,  image processing system,  image coding,  and sustained performace,  

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Summary: 
In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.