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A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning
Vijaya Gopal BANDI Hideki ASAI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Neural Networks
circuit simulation, gate level partitioning, waveform relaxation, transmission lines,
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This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.