Simulation of Power-Law Relaxations by Analog Circuits: Fractal Distribution of Relaxation Times and Non-integer Exponents

Kazuhiro SAITO  Michio SUGI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E76-A   No.2   pp.204-209
Publication Date: 1993/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Circuits and Signal Processing
Keyword: 
analog circuits and signal processing,  power-law relaxations,  fractal,  

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Summary: 
Power-law decay of current for the application of step-function voltage observed for amorphous materials can be expressed by an admittance sa(0a1) of a linear diode using complex angular frequency s. It is shown that power-law decay can be interpreted as a superposition of exponential decays having fractally distributed relaxation times and simulated using RC networks. By use of a similar manner, admittance s-b (0b1) showing the relation of duality can be simulated using RL networks. According to these methods, we can synthesize the admittance involving non-integer exponents systematically.