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An Improved Bipolar Transistor Model Parameter Generation Technique for High-Speed LSI Design Considering Geometry-Dependent Parasitic Elements
Yasunori MIYAHARA Minoru NAGATA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/02/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on High-Speed Analog Circuits and Signal Processing)
analog circuits and signal processing, computer aided design,
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This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.