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Compact Test Sequences for Scan-Based Sequential Circuits
Hiroyuki HIGUCHI Kiyoharu HAMAGUCHI Shuzo YAJIMA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
test generation, scan design, test application time, boolean function manipulation,
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Full scan design of sequential circuits results in greatly reducing the cost of their test generation. However, it introduces the extra expense of many test clocks to control and observe the values of flip-flops because of the need to shift values for the flip-flops into the scan panh. In this paper we propose a new method of generating compact test sequences for scan-based sequential circuits on the assumption that the number of shift clocks is allowed to vary for each test vector. The method is based on Boolean function manipulation using a shared binary decision diagram (SBDD). Although the test generation algorithm is basically for general sequential circuits, the computational cost is much lower for scan-based sequential circuits than for non-scanbased sequential circuits because the length of a test sequence for each fault is limited. Experimental results show that, for all the tested circuits, test sequences generated by the method require much smaller number of test clocks than compact or minimum test sets for combinational logic part of scan-based sequential circuits. The reduction rate was 48% on the average in the experiments.