A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal

Makoto IKEDA  Kunihiro ASADA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E76-A   No.10   pp.1666-1675
Publication Date: 1993/10/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

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This paper prsesnts a reduced swing signal data transmission method for the bus architectures in VLSIs, which consists of small size bus drivers of inverters, dual rail transmission lines, termination resistors and sense amplifiers for regenerating signal swing. The optimum value of signal swing and driving capacity of sense amplifier are given as functions of transmission line capacitance based on a criterion of areadelay2 for guideline. Using results of analysis, we propose a self-controlled data transmission module for the optimum reduced swing signal. Applying the method to a 32bit bus architecture, it is shown that total area, cycle time and total power consumption are 66,070[µm2], 0.90[ns], 32.2[mW], respectively, while those are 284,000[µm2], 1.12[ns], 173.4[mW], respectively, in the conventional chained buffer module. The proposed method is less noisy than the conventional chained buffer method.