The lmprovement in Performance-Driven Analog LSI Layout System LIBRA

Tomohiko OHTSUKA  Nobuyuki KUROSAWA  Hiroaki KUNIEDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E76-A   No.10   pp.1626-1635
Publication Date: 1993/10/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
process parameter,  wire parasitics,  device heat,  performance specification,  penalty function,  simulated annealing,  rip-up rerouting,  

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Summary: 
The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.