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High-Level Synthesis Using Given Datapath Information
Toshiaki MIYAZAKI Mitsuo IKEDA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
control circuit, scheduling, resource allocation, RTL, CFG, DFG,
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We propose a high-level synthesis method that uses data path information given by a designer. The main purpose of this method is to generate a control unit, one of the most difficult aspects of hardware design. In general, designers can specify data paths easily. Therefore, we believe that basing a method on specified data path information is the best way to synthesize hardware that more closely satisfies the designer's requirements. Moreover, a datapath-constrained scheduling algorithm can perform both "scheduling" and "resource allocation" at the same time. In particular, the resource allocation explicitly decides used paths as well as functional modules in each execution state. This cannot be done with previously reported algorithms.