A 2-Rail Logic Combinational Circuit for Easy Detection of Stuck-Open and Stuck-On Faults in FETs

Hideo ITO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E75-D   No.6   pp.894-901
Publication Date: 1992/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
easily testable design,  CMOS,  stuck-open fault,  stuck-on fault,  2-rail logic,  

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Summary: 
The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.