Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs

Kazuhiko IWASAKI  Shou-Ping FENG  Toru FUJIWARA  Tadao KASAMI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E75-D   No.6   pp.835-841
Publication Date: 1992/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
BIST,  aliasing probability,  multiple MISR,  M-stage MISR with m imputs,  binary symmetric channel,  

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Summary: 
MISRs are widely used as signature circuits for VLSI built-in self tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is grater than m. The aliasing probability as a function of the test length is analyzed for the compaction circuits for a binary symmetric channel. It is observed that the peak aliasing probability of the double MISRs is less than that of M-stage MISRs with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2dm and that for an M-stage MISR with m imputs is 2M if it is characterized by a primitive polynomial.