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Half-Micron LOCOS Isolation Using High Energy Ion Implantation
Koji SUZUKI Kazunobu MAMENO Hideharu NAGASAWA Atsuhiro NISHIDA Hideaki FUJIWARA Kiyoshi YONEDA
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/09/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Silicon Devices and Materials)
ion implantation, LOCOS, isolation, channel stop, ITF,
Full Text: PDF(519.5KB)>>
A new channel stop design for submicton local oxidation of silicon (LOCOS) isolation was presented. The n-channel stop was designed with boron implanation after forming LOCOS, while the p-channel stop was constructed with high energy phosphorus or arsenic implantation before or after forming LOCOS. These optimized channel stop designs can extend an isolation spacing to the submicron region without a decrease in junction breakdown voltage and an increase in junction leakage current. Narrow channel effects were found to be effectively suppressed by optimum channel stop design issues.