IEICE Trans - A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's

A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's

Koichiro ISHIBASHI Katsuro SASAKI Toshiaki YAMANAKA Hiroshi TOYOSHIMA Fumio KOJIMA

Publication
IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.572-575
Publication Date: 1992/04/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category:
Keyword:

Full Text: PDF>>

Summary:
An all-CMOS output buffer has been developed. The output buffer is composed of a voltage-follower and a source-follower circuit. The performance of the output buffer is characterized by a low-voltage operation of 1.7 V, a short delay of 1 ns, availability for the wired-OR connection, and adjustability to TTL, ECL, and a reduced swing level (RSL). The output buffer is incorporated into a 64-kb CMOS SRAM. This SRAM has achieved an access time of 4.3 ns at a supply voltage of -3.6 V.