High-Speed CMOS I/O Buffer Circuits

Manabu ISHIBE  Shoji OTAKA  Junichi TAKEDA  Shigeru TANAKA  Yoshiaki TOYOSHIMA  Satoru TAKATSUKA  Shoichi SHIMIZU  

IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.4   pp.569-571
Publication Date: 1992/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

Full Text: PDF(377.6KB)>>
Buy this Article

Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output curcuits.