High-Speed Sensing Techniques for Ultrahigh-Speed SRAM's

Hiroaki NAMBU  Kazuo KANETANI  Youji IDEI  Noriyuki HOMMA  Kunihiko YAMAGUCHI  Toshirou HIRAMOTO  Nobuo TAMBA  Masanori ODAKA  Kunihiko WATANABE  Takahide IKEDA  Kenichi OHHATA  Yoshiaki SAKURAI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.4   pp.530-538
Publication Date: 1992/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
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Summary: 
Two high-speed sensing techniques suitable for ultrahigh-speed SRAM's are proposed. These techniques can reduce a 64-kb SRAM access time to 71 89% of that of conventional high-speed bipolar SRAM's. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAM's for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 43% of conventional cells. A 64-kb SRAM with one of the sensing techniques is fabricated using 0.5-µm BiCMOS technology and achieves a 1.5-ns access time with a 78-µm2 memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAM's, which have been used as cache and control memories of mainframe computers.