Deep-Submicrometer BiCMOS Circuit Technology for Sub-10-ns ECL 4-Mb DRAM's

Takayuki KAWAHARA  Yoshiki KAWAJIRI  Goro KITSUKAWA  Kazuhiko SAGARA  Yoshifumi KAWAMOTO  Takesada AKIBA  Shisei KATO  Yasushi KAWASE  Kiyoo ITOH  

IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.4   pp.487-494
Publication Date: 1992/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

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A 0.3-µm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: 1) a Vcc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability, and layout area; 2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; 3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and 4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed-DRAM's, based on the 4-Mb design.