A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories

Yoshikazu MIYAWAKI  Takeshi NAKAYAMA  Shin-ichi KOBAYASHI  Natsuo AJIKA  Makoto OHI  Yasushi TERADA  Hideaki ARIMA  Tsutomu YOSHIHARA  

IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.4   pp.481-486
Publication Date: 1992/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

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To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.