A 100-MHz 2-D Discrete Cosine Transform Core Processor

Shin-ichi URAMOTO  Yoshitsugu INOUE  Akihiko TAKABATAKE  Jun TAKEDA  Yukihiro YAMASHITA  Hideyuki TERANE  Masahiko YOSHIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.4   pp.390-397
Publication Date: 1992/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

Full Text: PDF(759KB)>>
Buy this Article

The discrete cosine transform (DCT) has been recognized as one of the standard techniques in image compression. Therefore, a core processor which rapidly computes DCT has become a key component in image compression VLSI's. This paper describes a 100-MHz two-dimensional DCT core processor which is applicable to the real-time processing of HDTV signals. An excellent architecture utilizing a fast DCT algorithm and multiplier accumulators based on distributed arithmetic have contributed to reducing the hardware amount and to enhancing the speed performance. A layout scheme with a column-interleaved memory and a new ROM circuit are introduced for the efficient implementation of memory-based signal processing circuits. Furthermore, mean values of errors generated in the core were minimized to enhance the computational accuracy with the word-length constraints. Consequently, it features the fastest operating speed and the smallest area with its sufficient accuracy satisfying the specifications in CCITT recommendation H.261. The core integrates about 102K transistors, and occupies 21 mm2 using 0.8-µm double-metal CMOS technology.