A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI

Harufusa KONDOH
Seiji KOZAKI
Shinya MAKINO
Hiromi NOTANI
Fuminobu HIDANI
Masao NAKAYA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C    No.3    pp.280-287
Publication Date: 1992/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
PLL,  pull-in range,  oscillator,  ISDN,  primary rate interface,  

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Summary: 
A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.