Effects of Line Resistance and Parasitic Capacitance on Transmittance Distribution in TFT-LCDs

Kikuo ONO  Takeshi TANAKA  Jun OHIDA  Junichi OHWADA  Nobutake KONISHI  

IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.1   pp.93-100
Publication Date: 1992/01/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Displays
thin film transistor,  liquid crystal display,  parasitic capacitance,  resistance,  simulation,  

Full Text: PDF(673.4KB)>>
Buy this Article

Transmittance distribution along a horizontal line in LCDs addressed by amorphous silicon TFTs was investigated using measurements and calculations. Nonuniformity of the distribution, in which the transmittance increased with increasing distance from the left edge of the LCD, was observed in a 10 inch diagonal TFT-LCD. The cause of the nonuniformity was attributed to the decrease in voltage drop due to the gate source parasitic capacitance and the increase in gate voltage fall time due to large line resistance, based on the measurements of voltage drops in TFT test elements and calculations considering the decrease in voltage drop. The distribution could be improved by reducing the line resistance and parasitic capacitance in the actual LCD.