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Bonded SOI with Polish-Stopper Technology for ULSI
Yoshihiro MIYAZAWA Makoto HASHIMOTO Naoki NAGASHIMA Hiroshi SATO Muneharu SHIMANOE Katsunori SENO Fumio MIYAJI Takeshi MATSUSHITA
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on SOI (Si on Insulator) Devices)
Category: SOI LSIs
SOI, wafer bonding, polish-stopper, 256 kb SRAM 4 Mb SRAM cell,
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SOI technology has been developed for not only future ULSI, but also intelligent power ICs and sensors. In this paper the SOI fabrication process with wafer bonding and polish-stopper technologies, and its advantages for future ULSI are shown. And high crystal quality of SOI films fabricated with this method, and high speed performance of SOI devices and circuits, are shown from the data of 256 kb full CMOS SRAM chips. Moreover it is shown from the fabrication data of 4 Mb full CMOS SRAM cells that this technology has a large flexibility on device structure design. These results mean that our technology has great advantages for reduction of cell size and improvement of circuit performance.